A power level detection circuit of a flash memory device is configured to detect a voltage level of an internal power supply voltage (VDD) of the flash memory device and initialize the flash memory device when an internal power supply voltage (VDD) is greater than a critical (threshold) voltage level. In other words, when the power supply voltage (VDD) of the flash memory device is greater than a threshold voltage level, the power level detection circuit may be configured to generate control signals. The flash memory device may be initialized by the generated control signals.
During the initialization process of the flash memory device, signals may be applied to the flash memory device in order to obtain product information of the flash memory device. Response signals may be received from the flash memory device in response to the applied signals so that the product information of the flash memory device may be obtained.
FIG. 1 is a block diagram illustrating a layout design of conventional flash memory devices having power level detection circuits. As illustrated therein, the conventional flash memory device includes a memory cell array unit 100, a main circuit unit 120, an input/output pad unit 140, and a power supply pad unit 160. The memory cell array unit 100 includes a plurality of memory cells (not shown). Some conventional memory cells include floating gates and data may be stored/erased in the plurality of memory cells using erase and programming operations known to those having skill in the art. Furthermore, data may be read from the memory cell by applying a predetermined voltage to a control gate of the memory cell. As further illustrated in FIG. 1, the memory cell array unit 100 may be provided in a central region of the flash memory device and may occupy a significant portion of an area of the flash memory device.
The main circuit unit 120 is provided in a peripheral region of the memory cell array unit 100. The main circuit unit 120 is provided adjacent to a side of the memory cell array unit 100. The main circuit unit 120 includes a plurality of circuits for controlling operations of the memory cells (not shown). In particular, the main circuit unit 120 includes the power level detection circuit 125.
The input/output pad unit 140 is also provided in a peripheral region of the flash memory device. The input/output pad unit 140 is provided adjacent to the main circuit unit 120. The input/output pad unit 140 includes one or more input/output pads 145. Data may be input through or output from the input/output pads 140, for example, command signals and addresses may be received at the flash memory device through the input/output pads 140.
The power supply pad unit 160 is also provided in a peripheral region of the flash memory device. The power supply pad unit 160 is provided adjacent to the memory cell array unit 100. In particular, the power supply pad unit 160 is provided on an opposite side of the memory cell array unit from the main circuit unit 120 and the input/output pad unit 140. The power supply pad unit 160 includes a plurality of power supply pads, including a first power supply pad VDD pad 162 and a second power supply pad VSS 164.
As illustrated in FIG. 1, the power level detection circuit 125 is provided in the main circuit unit 120, which is spaced apart from the power supply pad unit 160. Thus, the power level detection circuit 125 is spaced apart from the first power supply pad VDD 162 and the second power supply pad VSS 164. In order to properly operate the power level detection circuit 125, power supply lines are provided between the power level detection circuit 125 and the power supply pads of the power supply pad unit 160 that electrically couple the power level detection circuit 125 to the power supply pads of the power supply pad unit. Accordingly, as a length of the power supply line increases, the level of the power voltage applied to the power level detection circuit 125 from the power supply pad unit 160 may be affected. For example, noise may be introduced and may cause the level of the power voltage applied to the power level detection circuit 125 to increase or decrease.
If the power supply lines are affected by noise, the power supply voltage applied to the power level detection circuit 125 may be unstable, which may cause abrupt changes in a short period of time. In particular, if the power supply voltage level rapidly drops below the threshold voltage and then rapidly rises above the threshold voltage, the power level detection circuit may not function properly, which may cause improper operation of the flash memory device.